System Test And Testable Design: Using ... — Digital

Verilog is used to describe the internal architectures of Built-In Self-Test (BIST) and Design for Testability (DFT) . This helps engineers evaluate hardware overhead and timing feasibility, which is critical for System-on-Chip (SoC) designs.

A distinguishing feature is the extensive use of the Verilog Programming Language Interface (PLI) . This allows for a mixed hardware/software environment where users can develop "virtual testers" to evaluate complex test strategies. Digital System Test and Testable Design: Using ...

The material is structured into two main parts: developing test environments and implementing testable hardware. Key Topics Covered Verilog is used to describe the internal architectures

The text treats testing and testability as integral parts of the digital design process rather than afterthoughts. This allows for a mixed hardware/software environment where

Gate-level faults, fault collapsing, and structural modeling in Verilog.

The book describes on-chip decompression algorithms in Verilog, providing a realistic look at how these impact overall chip area and performance. Key Technical Coverage